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K1S6416BCC
Document Title
4Mx16 bit Page Mode Uni-Transistor Random Access Memory
UtRAM
Revision History
Revision No. History
0.0 Initial Draft - Design Target Finalize
Draft Date
November 3, 2004
Remark
Preliminary
1.0
April 06, 2005
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 April 2005
K1S6416BCC
4M x 16 bit Page Mode Uni-Transistor CMOS RAM
FEATURES
* * * * *
UtRAM
GENERAL DESCRIPTION
The K1S6416BCC is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device supports 4 page read operation and Industrial temperature range. The device supports dual chip selection for user interface. The device also supports internal Temperature Compensated Self Refresh mode for the standby power saving at room temperature range.
Process Technology: CMOS Organization: 4M x16 bit Power Supply Voltage: 1.7~2.0V Three State Outputs Compatible with Low Power SRAM * Support 4 page read mode * Package Type: TBD
PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Speed (tRC) Power Dissipation Standby (ISB1, Max.) 120A(< 40C) 180A(< 85C) Operating (ICC2, Max.) 40mA PKG Type
K1S6416BCC-I
Industrial(-40~85C)
1.7~2.0V
70ns
TBD
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
VCC VCCQ VSS Row Addresses Row select Memory array
TBD
I/O1~I/O8
Data cont Data cont Data cont
I/O Circuit Column select
I/O9~I/O16
Column Addresses
CS1 CS2 OE WE UB LB
Control Logic
Name
Function
Name Vcc/VCCQ Vss UB LB NC
2)
Function Power Supply(core / I/O) Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) No Connection1)
CS1,CS2 Chip Select Inputs OE WE A0~A21 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O16 Data Inputs/Outputs
1) Reserved for future use 2) VCC and VCCQ should be the same level
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2Revision 1.0 April 2005
K1S6416BCC
POWER UP SEQUENCE
1. Apply power. 2. Maintain stable power(Vcc min. and VCCQ min.=1.7V) for a minimum 200s with CS1=high.or CS2=low.
UtRAM
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
Min. 200s VCC(Min) VCC VCCQ(Min) VCCQ

CS1
CS2
Power Up Mode
POWER UP(1)
Normal Operation
1. After VCC reaches VCC(Min.) and VCCQ(Min.), wait 200s with CS1 high. Then the device gets into the normal operation.
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
VCC(Min) VCC
Min. 200s
VCCQ(Min) VCCQ

CS1
CS2
Power Up Mode
Normal Operation
POWER UP(2) 1. After VCC reaches VCC(Min.) and VCCQ(Min.), wait 200s with CS2 low. Then the device gets into the normal operation.
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K1S6416BCC
FUNCTIONAL DESCRIPTION
CS1 H X1) X
1)
UtRAM
CS2 X
1)
OE X
1)
WE X
1)
LB X
1)
UB X
1)
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
L X1) H H H H H H H H
X1) X
1)
X1) X
1)
X1) H L X1) L H L L H L
X1) H X
1)
L L L L L L L L
H H L L L X1) X1) X1)
H H H H H L L L
L H L L H L L
1. X means dont care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCCQ+0.3V -0.2 to 2.5V 1.0 -65 to 150 -40 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
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Revision 1.0 April 2005
K1S6416BCC
PRODUCT LIST
Industrial Temperature Product(-40~85C) Part Name K1S6416BCC Function 70ns, 1.85V
UtRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage
1. TA=-40 to 85C, otherwise specified. 2. Overshoot: VCCQ+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Symbol Vcc Vss VIH VIL
Min 1.7 0 0.8 x VCCQ -0.23)
Typ 1.85 0 -
Max 2.0 0 VCCQ+0.22) 0.4
Unit V V V V
CAPACITANCE1)(f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current Output low voltage Output high voltage
Symbol
Test Conditions VIN=Vss to VCCQ CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to VCCQ Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIH or VIL IOL=0.1mA IOH=-0.1mA Other inputs=0~VCCQ 1) CS1VCCQ-0.2V, CS2VCCQ-0.2V(CS1 controlled) or 2) 0V CS2 0.2V(CS2 controlled) < 40C < 85C
Min -1 -1 1.4 -
Typ -
Max 1 1 40 0.2 120 180
Unit A A mA V V A A
ILI ILO ICC2 VOL VOH
Standby Current(CMOS)
ISB11)
1. Standby mode is supposed to be set up after at least one active operation.after power up.
ISB1 is measured after 60ms from the time when standby mode is set up.
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Revision 1.0 April 2005
K1S6416BCC
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCCQ-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCCQ Output load (See right): CL=30pF
AC Output Load Circuit
UtRAM
Vt=0.5 x VCCQ
50 Dout Z0=50 30pF
AC CHARACTERISTICS (Vcc=VCCQ=1.7~2.0V, TA=-40 to 85C)
Speed Bins Parameter List Symbol Min Common CS High Pulse Width Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Read Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width WE High Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z
1. tWP(min)=70ns for continuous write operation over 50 times.
70ns Max 70 70 35 70 25 25 25 20 25 -
Units
tCSHP tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW tBW tWP tWHP tWR tWHZ tDW tDH tOW
10 10 10 5 0 0 0 3 25 70 60 0 60 60 551) 5 0 0 30 0 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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K1S6416BCC
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
UtRAM
TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)
tRC Address tCSHP CS1 tAA tCO tOH
CS2 tCHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ tLZ Data Valid tOHZ
Data out
High-Z
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
A21~A2
Valid Address
A1~A0
Valid Address
Valid Address
Valid Address
Valid Address
tAA CS1
tPC
CS2 tCO OE tOE DQ15~DQ0
(READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. tOE(max) is met only when OE becomes enabled after tAA(max). 4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or needs to sustain standby state for min. tRC at least once in every 4us.
tHZ
tPA
Data Valid Data Valid Data Valid Data Valid
tOHZ
High Z
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K1S6416BCC
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tAW tCW CS1 tWR tCSHP tAW tCW tWR tWC
UtRAM
CS2
tBW UB, LB tWP WE tAS tDH tDW Data Valid tWHZ Data out Data Undefined tOW tWHZ tWHP tAS
tBW
tWP
Data in
tDH tDW Data Valid tOW Data Undefined
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC Address tAS CS1 tAW CS2 tBW UB, LB tWP WE tDW Data in Data Valid tDH tCW tWR
Data out
High-Z
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K1S6416BCC
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC Address tAS CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW tWR
UtRAM
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC Address tCW CS1 tAW CS2 UB, LB tAS WE tDW Data in Data Valid tDH tBW tWP tWR
Data out
NOTES (WRITE CYCLE)
High-Z
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
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Revision 1.0 April 2005
K1S6416BCC
PACKAGE DIMENSION
UtRAM
TBD
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Revision 1.0 April 2005

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